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authortcmal <me@aria.rip>2024-08-25 17:44:22 +0100
committertcmal <me@aria.rip>2024-08-25 17:44:22 +0100
commitdc1bcbbad887ccd710f386c6598eec17d9be5564 (patch)
tree0b858a0c48df4487c0d5815d24cfdb9c2c12e376 /stockton-render/src/draw/texture/image.rs
parent5998f9a8348306ba95e0262a9215808b1eeffb44 (diff)
fix(render): use coherent memory
applies to texture loading and vertex buffers. rather than flushing mapped memory.
Diffstat (limited to 'stockton-render/src/draw/texture/image.rs')
-rw-r--r--stockton-render/src/draw/texture/image.rs6
1 files changed, 2 insertions, 4 deletions
diff --git a/stockton-render/src/draw/texture/image.rs b/stockton-render/src/draw/texture/image.rs
index 2e0b27b..37e8ce8 100644
--- a/stockton-render/src/draw/texture/image.rs
+++ b/stockton-render/src/draw/texture/image.rs
@@ -186,7 +186,7 @@ impl LoadedImage {
device,
adapter,
BufUsage::TRANSFER_SRC,
- MemProperties::CPU_VISIBLE,
+ MemProperties::CPU_VISIBLE | MemProperties::COHERENT,
total_size,
)
.map_err(|_| "Couldn't create staging buffer")?;
@@ -201,9 +201,7 @@ impl LoadedImage {
let dest_base: isize = (y * row_size).try_into().unwrap();
img.copy_row(y as u32, mapped_memory.offset(dest_base));
}
- device
- .flush_mapped_memory_ranges(once((&staging_memory, Segment::ALL)))
- .map_err(|_| "Couldn't write buffer memory")?;
+
device.unmap_memory(&staging_memory);
}